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1下载：
串口实验，很好用，我还有verilog HDL
VHDL CPLD
EPM1270
源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
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2下载：
内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
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用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信
包括CP2102的配置 驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
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vhdl code for implementation of an UART
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altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
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用FPGA开发的串口通信的程序，代码是用verilog编写的，希望对大家有用！-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
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VHDL code for UART transmission & reception.
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vhdl code source for uart use
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uart - universal asynchronous receicer and transmitter source code using VHDL
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uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
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UART串口的VHDL源程序，希望对大家有用-UART serial port of the VHDL source code, we want to be useful
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UART 16750 source code for VHDL
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UART（通用串行收发器）的VHDL源代码，适合硬件工程师在FPGA内部实现多个UART-UART (universal serial transceivers), VHDL source code for hardware engineers in the FPGA to achieve multiple internal UART
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This iss VHDL source code for uart. I build and test it for SPARTAN-3E1600 and it work properly
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VHDL Code for UART Transmitter
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Code VHDL/Verilog for UART
FPGA: Xilinx, Altera-Code VHDL/Verilog for UART
FPGA: Xilinx, Altera...
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vhdl code for uart. data tx from pc to fpga nd vice versa
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UART code using VHDL for FPGA or ASIC
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VHDL CODE FOR UART IN DEEP MODIFIED
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UART transmission vhdl code, for nexys 3 fpga board
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