这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。-This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time,

MAX2 EPLD 的测试程序, VHDL语言编写.-MAX2 EPLD testing code, VHDL language.

在MAX2系列CPLD上实现脉冲宽度调制(PWM),完整的设计成程序和仿真结果。-In the MAX2 series CPLD to realize pulse width modulation (PWM), a complete design and simulation results into the program.

Alarm clock vhdl gdf for MAX2+plus