搜索资源列表
gps_tracking
- 澳大利亚新南威尔士大学研究的GPS接收机的FPGA跟踪模块的.v程序，包括载波跟踪环路、码跟踪环路、通道累加等模块。-The University of New South Wales, Australia, the study of the FPGA tracking GPS receiver module. V procedures, including the carrier tracking loop, code tracking loop, the channel accumulati
GPS.RAR
- 本工程包含了一个GPS接收机的基带处理模块，包括信号捕获和跟踪、电文解调等-The project includes a GPS receiver baseband processing modules, including signal acquisition and tracking, message demodulation
HDLC
- hdlc帧接收器 包含文件： 设计代码 测试代码 综合脚步 说明文档-HDLC frame receiver include file: design code test code Comprehensive documentation footsteps
up_buhuo
- 这是一个VERILOG接收端捕获模块，扩频码32倍，可以检测到相关峰-This is a VERILOG receiver capture module ,the spreader is 32,it can test the correlation peak
ETH
- 该系统通过顶层模块，调用4底层模块实现。4大模块底层模块为：cpu模块、发送模块、接收模块、mii模块-The system top-level module, called the bottom module 4. 4 large modules underlying module: cpu modules, transmit modules, receiver modules, mii module
ca
- 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
ofdm_Receiver_design
- OFDM Receiver design -OFDM Receiver design
micro-UARTsource_V
- UART(即Universal Asynchronous Receiver Transmitter 通用异步收发器)是广泛使用的串行数据传输协议。UART允许在串行链路上进行全双工的通信。-UART (ie Universal Asynchronous Receiver Transmitter Universal Asynchronous Receiver Transmitter) is a widely used serial data transfer protocol. UART allo
SONET_Framer
- The framer project assignment consists in developing a receiver for detecting SONET Frames patterns. Its basic functions are to receive a stream of serial data and based on SONET frames protocol build the sonet frames that carry the information da
top
- RS232串行通信，采用VHDL编程，由波特率发生器，接收器和发送器构成-RS232 serial communication using VHDL programming, by the baud rate generator, receiver and transmitter constitute
rs232_receiver
- VHDL implementation for an RS-232 receiver system.
Rs232Rxd
- Rs232 Receiver VHDL code
code_gen2
- GPS中C/A码生成电路，用于ＧＰＳ接收机中的跟踪和捕获。-GPS in the C/A code generating circuit for the GPS receiver to track and capture.
UART_DESIGN
- The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif
Rs232sourcecode
- Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to
Receiver
- 该程序是整个OFDM接收机的程序，希望对做这方面的朋友用些帮助，也希望朋友们和我一起探讨OFDM收发信机。-The program is the whole OFDM receiver process, hope to do in this area with some friends to help and also hope that friends and I explore OFDM transceiver.
Receiver
- OFDM通信系统接收端完整verilog代码-OFDM communication system receiver complete verilog code
Spread-Spectrum-Receiver-code
- 基于FPGA的扩频接收机（直扩）vhdl编写的，最好在quartus环境运行。-FPGA-based spread spectrum receiver (DS) vhdl prepared, the best environment to run in quartus.
rs232
- uart rs232 receiver and transmiter
all-digital-fm-receiver
- all digital fm receiver using vhdl programming language project for electronics and communication engineering students.