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shifter
- 用vhdl实现双向移位寄存器 仿真环境MAXPLUS-II，QUARTUS--bidirectional use VHDL simulation environment shift register Segments-II, QUARTUS-
CNT_24
- 用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-
pulse_change
- 用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS--use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-
RS232-for-vdhl
- RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
lift
- VHDL driver of lift in building. Result is presents on LED segments[decimal value].
list_ch03_12_hex2led
- This VHDL convert a hex number to seven segments codes.
Lab1
- My first project written in Quartus II by using VHDL, executed some tasks that display word on 7-segments LED through the simulated 5-to-1 multiplexer. My code is easy to acquire and may be help usefull.
display7segmentos
- Dislay 7 segments -Dislay 7 segments ..........................................
keyboard_vhdl
- ps2 keyboard with encoding ascii code to 7-segments screeen. LIBRARY ieee USE ieee.std_logic_1164.all USE ieee.std_logic_arith.all USE ieee.std_logic_unsigned.all ENTITY klawa IS PORT ( keyboard_clk, keyboard_data, clock_25MHz,
bcd_to_7segmentos
- bcd to 7 segments display tested on xboard xilinx, all code developed on vhdl
Displayer
- VHDL编写的针对八段数码管的显示译码电路。实现动态扫描输出小时、分钟和秒。是基于CPLD开发板设计的一个数字钟的一部分。-Programmed with VHDL.The decoding and displaying circuit for 8-segments displayer.It outputs the data of hour,minute and second in order with dynamic scaning method.It is one of my total 9
shunmaguanxianshidianlu
- 用VHDL语言编写一个八位数码管显示电路，每个数码管的八个段分别连在一起，八个数码管分别由八个选通信号选择。被选通的数码管显示数据，其余关闭-With the VHDL language to write a eight digital tube display circuit, each digital tube eight segments are connected together, the eight digital tube are respectively composed of
Vsteepper_motH
- 步进电机 VHDL 控制，整步 半半步 细分 actel FPGA使用 -VHDL control of stepper motor, whole step, half half step segments actel FPGA use
7 Segment Interfacing
- This source is used for control 7 segments on FPGA board. It is written by VHDL
ISE_lab5
- 七段数码管的VHDL源代码 适合本科生学习使用-Seven segments of the VHDL source code for undergraduate learning to use
visualitzador7segments-20170516T144823Z-001
- Code in VHDL of a segments visualizer (used for a clock)
7Seg. Display
- 7 Segments Display - VHDL Project
DecHex7Seg
- Decoder Hex 7 Segments - VHDL Project