搜索资源列表
my_dcm
- 在xilinx的ISE环境中配置一个DCM组件，可进行查看程序运行的时间。通过串口与终端设备相连
dcm_test2
- xilinx fpga 倍频的例子，包含整个工程， 如果去用ISE 实现倍频，dcm 用法-xilinx s FPGA dcm example
DCM
- Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
dcm2
- 基于Xilinx Vertex4的可综合的二级DCM模块源代码，可生成400Mhz时钟信号-Based on Xilinx Vertex4 of two integrated DCM module source code, can generate 400Mhz clock signal
BUFG_CLK2X_FB_SUBM
- xilinx DCM 应用的源代码，完全可用-xilinx DCM application source code, fully available
BUFG_CLK0_FB_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLK0_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLK2X_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLKDV_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
DCM_12M_1M
- xilinx下DCM输出12Mhz和1Mhz-Verilog DCM xilinx ISE
Xilinx_DCM
- 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
ISE_lab15
- 利用XILINX官方例程熟悉PicoBlaze软核；熟悉使用Architecture Wizard配置和初始 化DCM；掌握使用核生成器（Core Generate）生成一个IP核，并将其插入到设计中。-XILINX official familiar with the routine use of soft-core PicoBlaze familiar with the Architecture Wizard configuration and initialization DCM
dcm
- Xilinx的V4FPGA数字时钟管理模块的底层原语实现代码，硬件上跑通- The Xilinx V4FPGA digital clock administration module s first floor primitive realizes the code, on the hardware runs passes
double_dcm
- 这个主要是在xilinx FPGA中双DCM连接的问题，这个问题网上资料很少，自己研究后并且仿真之后可以实现两个dcm的正常工作，实现倍频和时钟的反相-This is mainly the double in xilinx FPGA DCM connection problem which little information online, their own studies and simulation can be achieved after the normal work of the
ddr_100Mhz_2011.03.12
- 这个工程是用xilinx的MIG生成的对于spartan 3E的实验板的ddr的控制器，我已经能够在上面修改之后加入自己的思想，包括两个dcm的模块。-This project is the MIG generated by xilinx spartan 3E development board for the ddr controller, I have been able to modify the above by adding his own ideas, including the t
DCM
- 详细介绍了基于XILINX公司FPGA时钟管理模块DCM的IP核生成和使用-xilinx ise DCM
TEST1
- Xilinx FPGA中DCM的用法，采用创建一个IP的方法。-Use DCM module in Xilinx FPGA.Creat a IP module to do it.
vtc_demo
- Xilinx DCM phase change interface for spartan 6
Xilinx_DCM.zip
- xilinx DCM功能说明文档，介绍了DCM的结构以及使用方法。,xilinx DCM function documentation describes the structure and use of DCM.