搜索资源列表
xilinx_ise_14
- this the xilinx_ise_14 s license!after you have setuped the software,the license will very helpfull! the xilinx_ise_14.lic file ,xilinx_ise_14 license-this is the xilinx_ise_14 s license!after you have setuped the software,the license will very he
USB
- 基于XILINX+ISE+14.1的usb协议设计-Usb protocol design based on XILINX+ISE+14.1
music
- 利用FPGA模拟弹钢琴的Verilog代码。在Xilinx ISE 14.3 编译通过-Using FPGA Verilog code simulation play the piano. Compiled by Xilinx ISE 14.3
lic_Xilinx_ISE_Vivado
- 这是Xilinx ISE 14.X以及vivado、vivado_hls的license，亲测可用-Xilinx ISE 14.x vivado, vivado_hls license, pro-test available
step
- 步进电机控制的FPGA代码，包括方向控制模块、激磁方式选择模块、定位模块以及输出脉冲。在Xilinx ISE 14.2环境下仿真验证过。-FPGA code stepper motor control, including directional control the module excitation mode selection module, positioning module, and the output pulse.
multi_cpu
- 用xilinx ISE 14.3开发的多周期CPU系统，开发语言为verilog HDL.仿真调试与实际测试均已通过-Using xilinx ISE 14.3 development of multi-cycle CPU system, development language for verilog HDL. Simulation debugging and practical tests have passed
xilinx_ise
- Xilinx ISE 14.4 Lincense，实测可用-Xilinx ISE 14.4 Lincense, actual available
Micrium_Microblaze_uCOS-II-AXI
- 支持xilinx ise designer 14.x的microblaze AXI总线 ucosii操作系统。-Support xilinx ise designer 14.x for microblaze AXI bus ucosii operating system
my_uart2
- 基于FPGA的串口通信源代码。已经经过调试助手测试，-Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Sum
hash_function_sha3
- The synthesis software is Xilinx ISE version 14.4. The low throughput core has been synthesized targeting a very cheap Spartan 3 (XC3S5000-4FG900). This project is licensed under the Apache License, version 2. I prefered on the internet
led_shift
- 在xilinx的ISE上写的LED灯移动的verilog程序-a verilog code for led-shifting which writed with ise 14.2
Counter3
- 基于Xilinx 的ISE 14.7 的计数器程序，包含testbench文件和约束文件-Based on the Xilinx ISE 14.7 Counter program, including testbench and constraints files
IP_COE_Abs2Rel
- 编程辅助软件，将Xilinx ISE 14.x IP核含有的COE文件从绝对路径改成相对路径-Progrmming assisting software, Xilinx ISE 14.x IP core have COE file absolute path change into relative path
Seven_segment_display
- SEVEN SEGMENT DISPLAY, ON VHDL, ISE DESIGN SUITE 14.7, XILINX
dwt
- Running: C:\Xilinx_Installed\14.3\ISE_DS\ISE\bin\nt\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe -pr
xilinx_ise_14.4_licence
- 14.4 xilinx ise licence
xilinx_ise
- xilinx ISE 14.7 license文件 就是破解(xilinx ISE 14.7 license crack)