查看会员资料
用 户 名:秦***
发送消息- Email:用户隐藏
- Icq/MSN:
- 电话号码:
- Homepage:
- 会员简介:
最新会员发布资源
logic
- Verilog HDL逻辑与计算机设计基础实验全部试验报告,包括寄存器,定时器,全加器,同步时序电路,译码器等的实验。-Verilog HDL logic and computer design basic experiment all test reports, including registers, timers, full adder, synchronous sequential circuits, decoders and other experiments.