查看会员资料
用 户 名:Ro***
发送消息- Email:用户隐藏
- Icq/MSN:
- 电话号码:
- Homepage:
- 会员简介:
最新会员发布资源
cnt60
- 60秒加一计数器,实现0到59秒计时。可以参照此例编写一个FPGA时钟,代码用VHDL编写。开发环境为quertues ii9.1.-60 seconds with a counter, to achieve 0 to 59 seconds. Can refer to this case to write a FPGA clock, the code written in VHDL. Development environment for quertues ii9.1.