资源列表
单片机坐标定时器实验
- http://www.edacn.net/cgi-bin/forums.cgi?forum=7&topic=9127下,则R3~R0的输出信号中会有一个为1,但我们还是是无法确定哪一个键被按下,必須要从R3 ~R0 的输出信号与C3~C0的扫描信号共同決定那个按键被按下. 编写VHDL的构思: 外部接口包括: a. INPUT脚 : CLK , R3~R0. b. OUTPUT脚 : C3~C0 , DATA3~DATA0(辨别出的按键值). -7topic http://ww
mp3if
- 通过CPLD将8位并行数据转换为串行数据并可以采用I2C方式与其他器件连接,可以用于MCU需要与提供I2C接口器件通信的场合。-through CPLD to eight parallel data into serial data and methods can be used I2C connections with other devices, which can be used to provide MCU with I2C Interface Communications occasi
I2C总线控制器 Xilinx提供
- 用Verilog HDL实现I2C总线功能,对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.
lightW
- 一個LCD燈的小程序。不是我寫的。我只負責了調試。適用在ACEXEP1K30QC208-3上。我跑了SIMULATOR,管腳連接標示了。我也下在電路板上試過了,沒有問題。要用到實驗板上的兄弟們把CLK1改到TESTOUT3或者0就好了。綫幫助新手,人人有責。-a small LCD lights procedures. I did not write. I am only responsible for the debugging. Apply in ACEXEP1K30QC208-3 on.
intro_to_quartus2_chinese
- 介绍quartus II 汉语教程,非常难得,-A Chinese introduction to quartus II.
Figure_Models
- James Armstrong VHDL Design , source code
des-verilog
- des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
clock_time
- 本文件解压后clock_time.vhd采用编程环境maxplusII,完成时间秒定时、记时,设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
示例(vhdl)
- vhdl 实例 通过实例学习vhdl 编程-VHDL examples examples to learn VHDL programming
UART设计参考
- 软 件 设 计 者 必 看 UART 设计 参考-software designers Watchable UART reference design
ClkScan
- 此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块,一个提供同步信号(H_SYNC和V_SYNC)及像素位置信息;另一个接收像素位置信息,并输出颜色信号。这样便于进行图形修改,同时也容易实现- This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature
qdq_new
- 采用Verilog HDL设计,在掌宇智能开发板上得到实现 根据抢答器的原理,整个电路可划分为三部分:采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on the palm space intelligence development board to snatch the answering principle, the entire electric circuit may divi