资源列表
describe_0414
- 基于FPGA的乐曲发生器设计 -Design of FPGA-based music generator music generator design based on FPGA
Four-binary-adder
- 程序1：4位二进制加法计数器（EDA实验中用到的)-Four binary adder
ycbcr-422-to-444
- ycbcr 422 to 444格式转换-YCbCr 422 to 444 format conversion
fenpin
- VHDL编写的分频器，占空比为1:1，可以根据需要，修改计数器，完成不同频率的分频-Divider in VHDL, the duty cycle of 1:1, as needed, modify the counter, complete different frequency divider
Fitter
- 32bit fitter vhdl code from an old project
Anne
- write "AnnE" with 7 segment display using vhdl code at spartan 3e
ram_dual
- Design of a DRAM of any bit
mux3_case
- implementation of multiplexer using case statements in verilog
coder_8_3
- 8 - 3 线 优 先 编 码 器 。高电平有效，高位到低位置位。高位优先级高于低位-8 3 line priority encoder. Active high, high to low bit. High priority than low
interpolate4
- 调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据-4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data
logic
- Verilog descr iption for cell logic
adder16_2
- 两个16位的二进制数相加，分别是高位和高位相加，低位和低位相加。-Two 16-bit binary numbers together, were added to high and high, low and low sum.