资源列表
bpsk1
- 上传的包括BPSK,AGC,LCD1602和12846的显示代码和一个自己写的1602内核，代码全部得到验证，都可以使用！-Uploaded including BPSK, AGC, the LCD1602 and 12846 display code and a 1602 write kernel code all been verified, you can use!
binary_to_decima
- 8位全加器的VHDL描述，可用MAX+plusⅡ运行测试-8-bit full adder of the VHDL descr iption，MAX+ plus Ⅱ can be used to run test
adder8
- Vrilog HDL 八位加法器源程序-8 adder Vrilog HDL source
XilinxISEDesignSuite12.1
- Xilinx ISE Design Suite 12.1 cd key
univ
- universal binary counter
CPU2A03
- 任天堂nes系统 cpu处理器，2a03部分代码，希望大家用得着-Nintendo nes system cpu processor 2a03 part of the code, I hope you need it
ds
- Verilog语言，实现移相,输入方波TA，输出移相后T-Phase shifted square wave TA, the phase-shifted output TAA
mux3_if_else
- implementation of multiplexer using if else statement in verilog
annie5
- led汉字滚动显示，可根据不同的设定显示汉字-led scrolling display of Chinese characters can be set according to different display of Chinese characters
MCUBUS
- 实现MCU与单片机的通信借口 特别强调了对三态门的VHDL编程-MCU VHDL
sipo_reg5
- VHDL语言描述具有同步清零的5位串行输入并行输出移位寄存器代码-VHDL language to describe the clearing of 5 with synchronous serial input parallel output shift register code