资源列表
yimaqi
- 基于FPGA环境开发，采用3-8译码电路原理。制作而成的译码器- FPGA-based development environment, using 3-8 decoder circuit schematic. Made of a decoder
link_act_decode
- Verilog语言下讲LINK/ACT信号转换为 LINK信号，即讲闪烁的信号转换为固定电平-Under the Verilog language speaking LINK/ACT LINK signal is converted to a signal, that signal is converted to speak flashing fixed level
Alu_Solution
- Solution for 16bit ALU component in vhdl.
UCOS-II
- 基于FPGA的实验 UC\OS-II操作系统移植，使用SOPC软件及其配置方法，掌握其在NIOS II IDE 中的简单使用。-FPGA-based experimental UC \ OS-II operating system migration, the use of SOPC software and its configuration to grasp the NIOS II IDE in the simple use.
Decoder
- This a basic code for the decoder based on verilog.-This is a basic code for the decoder based on verilog.
FJYFP
- 用vhdl语言编写的分频程序，一个50分频，一个100分频，一个19200分频-Written by vhdl divide program, a 50-band, a 100 frequency, a frequency of 19200
HALF-ADDER-VHDL
- 用硬件描述语言编写的8位全加器代码，很实用通过对代码的编译和波形检测显示出此设计也是完全符合要求的，并且和设计的电路图一样，也达到相同的效果。-Using hardware descr iption language preparation 8 bits QuanJia implement code, is very practical through the code compiler and waveform test shows the design is fully meet the r
Random_counter
- Random_counter for fpga
src_gen
- 使用VHDL语言产生m序列，用于通信系统的随机信源-To generate m sequence with HHDL,whcih is used as random source in communication system
lightgc
- verilog code for guide light
counter
- Counter code in verilog for counting till 59.-Counter code in verilog for counting till 59.99
2ASKtiaoshi
- 2ASK verilog 解调程序，二进制移幅键控解调程序 -2ASK verilog progarm