资源列表
1111111111
- 计算机网络构建与安全课件 计算机网络构建与安全课件
CLOCK_co-design_of_C_and_Verilog
- A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
128Mb_ddr
- 128Mb DDR verilog源程序
ADT_VC
- 本程序为盛博ADT系列接口系列的实例程序，可以进行16通道数据采集
Find_medium_value_co-design_of_C_and_Verilog
- A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.
ScanSample
- 使用LEADTOOLS14.5和VB，利用TWAIN接口进行扫描的示例，可进行各种扫描参数的参数
RGB_color_transform_gray_level_co-design_of_C_and_
- to use verilog code and c to translate a RGB bmp image(512*512) to a gray level image
show_your_student_ID_number_co-design_of_C_and_Ver
- As the source code name, this code is writing in Verilog and also inside the folder there is a c code to see the simulation results from verilog.
Traffic_sign_co-design_of_C_and_Verilog
- This is an extension of sign example. You can design your own traffic sign by using Verilog. And the result from Verilog can be seen by the attached C file.
chipgenius
- USB HUB 芯片资料,开发参考，维修，试验用--来自其他网络
javachat
- 这是一个采用JAVA做的聊天系统，没有用数据库，直接进行聊天
xhu
- 这是自己做的一个FLASH文件，主要显示的是AA大学的图片及其历史