资源列表
16位乘法器
- 自已写的一个16X16的乘法器，速度比较慢。初学者练习练习！-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!
能综合的YCrCb2RGB模块（verilog)_采用3级流水线
- 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
自定义逻辑PWM的例子
- 是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。-is a VHDL language with the PWM procedures can be used to facilitate connections and nios, nios to achieve a functional extension.
ref-sdr-sdram-vhdl
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
PINPAN
- 乒乓游戏 ，led流水灯控制乒乓球，按键控制甲方已方操作。详细说明看readme-ping-pong game, led lights to control water table tennis, has been chosen to control keys to operate. Details see readme
8位相位相加乘法器
- 8位相 加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages
altera的IP源码
- Altera的IP源码8259，只需打开就能实现-Altera IP source 8259, will be realized only open
CORDIC
- 用verilog写的CORDIC算法实现，很适合做超越函数的运算。通常用于实现正弦乘法，或者坐标变换。-The cordic arithmetic implemented by verilog is adapted to exceed function.It is usually used to implement sine multiplication or coordinate tuansform.
Verilog2C++
- 将Verilog代码转换成C++代码的软件，C源代码。-soft for changing Verilog code to c++ code ,c code
VHDL 程序举例
- VHDL经典编成程序。有大概100个程序。包括键盘扫描等。- these are typical program of VHDL.there are almost 100 pieces of program.including program about keyboard scanning.
I2C总线控制器 Xilinx提供
- 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.
intro_to_quartus2_chinese
- 介绍quartus IＩ 汉语教程，非常难得，-A Chinese introduction to quartus II.