资源列表
analog_and_mixed_signal_ic_design
- 模拟与混合信号集成电路前端设计培训,内含ADC设计，verilog A, SPICE,设计方程\方法等(Analog and mixed signal ic front end design tutorial, example ADC design. including Verilog A, SPICE and design equations for AMS circuit design.)
ISimChipScopeIPCore
- 这是我都记得FPGA资料，里面有ISIM,ChipScope,RAMorROM IPCore使用的教程，对于学习是很好的参考。(I remember FPGA data, there is an ISIM the ChipScope RAMorROM IPCore to use the tutorial, is a good reference for learning.)
Bayer2RGB
- Bayer 转RGB Verilog代码实现。。5*5 窗口。在工程中应用的(Bayer to RGB Verilog code implementation. 5*5 window. Applied in Engineering)
WhiteBalance_10bit
- 模块功能：通过白平衡消除由光照带来色差（绿雾） 模块输入：亮度增益输出R,G,B三通道像素值（double） 模块输出：白平衡后R,G,B三通道像素值（double）(Module function: to eliminate chromatic aberration (green fog) caused by illumination through white balance. Module input: brightness gain output R, G, B three c
uart_rx
- Verilog实现的RS232发送和接收程序，有完成的verilog代码，testbench等。(UART send and receive verilog code, including verilog source code, testbench etc.)
基于GMＲ-1系统下行链路的π_4-CQPSK解调方法
- pi4 qpsk的付费论文，讲述FPGA实现的，非常值得学习(Pi4 QPSK's paid papers will be very useful for FPGA.)
VerilogHDL解码DS18B20
- DS18B20解码代码，verilogHDL实现。
Eagle_DataSheet_v1.9 - EG4X20BG256.pdf
- Eagle DataSheet v1.9 - EG4X20BG256
TR4_GPIO1_D8M
- 友晶科技的TR4的开发板，接上D8M摄像头的程序 输出的是MIPI解码后的10位数据 内带signaltap仿真结果和连接图(The development board of TR4, the D8M camera program. The output is the 10 bit data after MIPI decoding. include signaltap simulation results and connection diagrams)
teacher_uart
- 由verilog编写的uart收发模块，能够在串口助手发送字符，并在数码管上显示，开发板为basys3 内置约束文件(The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3)
DDR_sdram
- 文件里有DDR3/DDR4 sram的verliog模型，而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)
FIFO_UVM
- fifo uvm this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output(this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving prop