资源列表
MT29FxxG08xx.rar
- MT的NAND FLASH MT29FxxG08xx系列的Verilog仿真模型，包含详细说明，试验证明，非常准确。,MT of the NAND FLASH MT29FxxG08xx series of Verilog simulation model, contains a detailed descr iption, testing proved very accurate.
CORDIC16.rar
- 16次迭代的CORDIC算法，精度很高，可应用于计算反正切值,16 iterations of the CORDIC algorithm, high accuracy, can be applied to calculate arctangent
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
I2S
- 用verilog实现的 I2S 源码，可以直接通过Quartus运行-I2S implementation by verilog source code can be run directly through the Quartus ~ ~
FPGA-usb-control
- USB 68013 通用固件 和配套上位机程序以及下位机FPGA程序verilog 可实现USB高速通信-USB 68013 generic PC firmware and supporting procedures and lower computer USB FPGA program can achieve high-speed communications
PCIe_DMA_Freeware
- Xilinx PCIe 带 DMA，烧入V5平台验证过的，内有pdf文档详细的教程，windows驱动和应用界面也在里面，全面的一目了然的资料-Xilinx PCIe with DMA, burning into the V5 platform, verified with a pdf document detailed tutorial, windows driver and application interfaces are inside, comprehensive informatio
AM-FM-software-radio
- 用FPGA开发AM，FM接收机的论文，外国人写的，我已实现-FPGA development using AM, FM receiver paper, written by foreigners, I realized
Verilog_SRAM.rar
- 使用Verilog写的SRAM的控制程序，仅供参考！,The use of the SRAM write Verilog the control procedures, for reference purposes only!
用VHDL编写的计算器
- 用VHDL编写的计算器：能实现简单的加减乘除四则运算 ,Prepared using VHDL Calculator: able to achieve simple addition and subtraction, multiplication and division 4 computing
DUC.rar
- 基于XILINX ISE下的数字上变频设计，其中用到了XILINX的乘法IP。已经通过工程实用，好用。,XILINX ISE based on frequency of figure design, use one of the XILINX multiplication IP. Has passed the project practical, easy to use.
ml506_lab_resources.zip
- xilinx 开发板ML506 示例代码集合。,Xilinx ML506 development board sample code collection.
fifo
- 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave