资源列表
gtech_lib
- GTECH library cells file. Its very usuful in asic synthesis
verilogfile
- 设计一个同步FIFO，该FIFO 深度为16，每个存储单元的宽度为8 位，要求产生FIFO 为 空、满、半满、溢出标志。请采用可综合的代码风格进行编程。-16*8bit fifo
hdl
- 使用FPGA完成对直流无刷电机的控制的源代码-Use the FPGA to complete the brushless DC motor control source code
dsp-config-fpga
- TI 6713通过spi口配置fpga的源代码。-program for TI S 6713,used for configure of FPGA BY SPI INTERFACE
FM24CL16_I2C
- 使用STM32来访问I2C接口的铁电存储器，FM24CL16，2K字节-STM32 to access the I2C interface using ferroelectric memory, FM24CL16, 2K bytes
usb2.0 fpga
- 免费的USB2.0源码(支持Xilinx和Alteral的FPGA),用vhdl语言实现。-Free USB2.0 source (supports Xilinx and Alteral the FPGA), using vhdl language.
scoreboard
- MIPS体系结构用verilog实现的记分牌算法，标流水线-Architecture implemented using verilog scoreboard algorithm, standard line
bch
- 用C语言实现BCH码的编码和译码，译码是用BM迭代算法。-BCH codes in C language coding and decoding, iterative decoding algorithm with BM.
Analog-Circuits--4Ed(Tongshibai)
- 模拟电子技术基础第四版，带课件和习题答案，童诗白著，带书签-Analog Circuits 4th Edition
PCIE_V5
- PCIE_V5是一个完整的VC工程，用于xilinx Virtex5 FPGA的PCIe板卡下DMA数据读取，只能在Win xp下运行，板卡的驱动程序需要安装WinDriver-PCIE_V5 is a VC++ project, which is used to ingress massive data from PCIe board based on Virtex5 FPGA through DMA interface. Install Windriver to offer the boar
bch_verilog
- bch(255,239)编码算法的verilog实现，综合仿真通过，与matlab仿真的结果一致-bch(255,239)，using verilog
digital_tsmc018
- 180nm数字教学库，内含各种标准数字单元-180nm digital lib for education, including standard cells