资源列表
3U-CPCI-PCB-Template
- 3U CompactPCI PCB 模板，使用工具为Altium Designed 9-PCB template of 3U CompactPCI with Altium Designed 9
QPSK
- 这是关于QPSK调制解调的VerilogHDL语言的代码，还有用Modelsim仿真的工程文件。testbench都已经写好了。-This is the QPSK modulation and demodulation of VerilogHDL language code, as well as with Modelsim simulation project file. testbench have been written.
adder_carry_chain
- 使用verilog语言实现进位链加法器,quartus下编译，并使用modelsim进行了验证，内含carry_chain.v代码文件以及testbench文件-use verilog language,carry_chain adder
flash_spi_master_axi
- 使用xilinx 的QUAD spi core 对flash芯片进行控制的代码。-Using xilinx s Quad SPI core to control the external flash device.
扩频通信的Verilog工程
- 扩频通信的Verilog工程，对从事无线通信的工程人员有参考作用。(Spread spectrum communication Verilog project, engaged in wireless communications engineering staff reference.)
AXI slave
- 使用verilog语言实现了AXI总线通信协议的从机部分(The slave part of AXI bus communication protocol is realized by using Verilog language)
vc2015_x64_14.0.24215
- windows 7 安装VIVADO 需要(Microsoft Visual C++ 2015 Redistributable(x64) - 14.0.24215)
ahb
- verilog实现AHB总线上的主从控制，在fpga上验证通过(Verilog realizes master slave control on AHB bus and verifies it on FPGA)
MVB通信架构和流程图
- MVB架构流程图。MVB开发用，大连海天资料(MVB development, Dalian Haitian data)
基于verilog的CAN总线代码
- 用Verilog实现CAN总线，经过仿真验证，可以直接用！
SPI_UVM_VIP
- SPI协议的芯片验证VIP,用UVM搭建平台验证代码(Chip verification VIP of SPI protocol, build platform verification code with UVM)
polyPhaseFilter
- 数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)