资源列表
PushButton_Debouncer
- KEY INPUT DEBUNCE VERILOG-KEY INPUT DEBUNCE verilog
1
- 加法器的VHDL代码，可以在很多地方直接应用
pt
- FPGA display red,blue and green color
m_divider_int
- 14bit pipeline 除法器，在Xilinx V5上可以跑到100M，输出延时3cycles-14bit 100M pipeling divider
Caumajo_hybem_tlacidlami
- Arduino LCD text output & input buttons
clock
- 该代码用verilog语言编写，实现24小时时钟计时，时、分、秒，输入为1HZ时钟-The code using verilog language to achieve a 24-hour clock time, hours, minutes, seconds, the clock input 1HZ
comparator
- comparator it comparea two input and give its output
i2c-(2)
- de2 board using fpga plat form verilog code for i2c concept
LTC1450
- 一个DAC（LTC1450）用c8051f020调试成功的c语言代码-A LTC1450 (DAC) with the success of c8051f020 debugging c language code
CECtrls
- WinCE 版 Edit 编辑控件再封装，在添加文本时速度非常快。-editor control for Windows CE.
fill
- 数据块填充程序：将片外RAM 7000H-70FFH单元按一定规律填充-Data block filling procedure: piece of external RAM 7000 h- 70 FFH unit according to certain rule filling
CLOCK
- 用VHDL语言实现时钟功能，可进行分和秒设置-Clock function using VHDL, can be set up in minutes and seconds