资源列表
7
- verilog 写的 “梁祝”乐曲演奏电路-verilog wrote " The Butterfly Lovers" music concert circuit
serial_implementation
- VHDL 实现 有限冲击响应滤波器的设计（串行式）-VHDL realization of finite impulse response filter design (Serial)
sell
- 基于FPGA的自动售饮料机，包含2.5元、3元两种选择-FPGA-based beverage vending machines, including 2.5, 3 yuan two options
fsmd_debounce_exp
- vhdl debounce circuit
VHDL-test-code-general-register
- VHDL实验代码：通用寄存器组，这是一个基于VHDL开发的程序，非常的实用-VHDL test code: general register, which is a VHDL-based development process, a very practical
Digital-Clock
- FPGA数字跑表代码 Digital Clock-Digital Clock
TC35-Module
- GSM短信模块，可以同单片机连调，可发短信，调用的话改个号码就可以了-GSM SMS module with microcontroller sandhi can send text messages, calls, you can change the number
PWM_Basic
- 基于ADUC7060的PWM波产生程序。 ADUC7060 是ARM7TDMI内核。-Based ADUC7060 PWM wave generator. ADUC7060 is the ARM7TDMI core.
Driver
- MAX186芯片初始化 PIC16F877A 内部AD初始化-MAX186 init
SDRAMping-pong-memory-structure
- 双口RAM 的乒乓存储结构（芯片型号CY7C09279） 应用场合为FPGA向双口RAM不断写入数据，PCI总线从RAM读取数据。[已调试验证]-Dual-port RAM, ping-pong memory structure (chip model CY7C09279) applications for the FPGA to the dual-port RAM write data continuously, PCI bus read data from RAM. [Debugging
BitBand
- STM32F4的GPIO的位带操作头文件,包含改头文件后即可在程序中是用GPIO的位操作.详见源码中的宏定义.-STM32F4 bit with the operation of the GPIO header files can be used in the program after the operation bit GPIO header file containing the change. Detailed source code in the macro definition.