资源列表
12684
- 12864 7904芯片lcd源码程序-128,647,904 chip lcd source program
JungleRoads1251
- 北大 poj 上 题目：JungleRoads1251的解题源码-JungleRoads1251 answer
com2pgm
- This program is wrote by Fujian Shi(fieagle@yahoo.com.cn)It can transform the com file to pgm file ,you can watch the picture-wrote by Fujian Shi (fieagl e@yahoo.com.cn) It can transform the file t com o pgm file, you can watch the picture
MFSK
- 基于VHDL硬件描述语言，完成对基带信号的MFSK调制,源码
TEST7
- 这是一个键盘扫描的程序 没有去抖电路 但是还是很好用的 我测试过 很好用的-This is a keyboard scanning procedure did not go to shake or a good circuit but I tested used a very good use
statemachinecontroller
- it is a vhdl code for a state machine controller
syn_fifo
- 很好的同步FIFO设计代码，和大家分享一下，多多交流，不是我自己写的-Good synchronous FIFO design code, and share with you some more exchanges, not my own writing
fet440_uart01_09600
- MSP430 設定UART鮑率為96-UART MSP430
jiaotongdengkongzhi
- 交通灯实现正常时序控制及急车强通两种控制方法。启动开关接通时，交通信号按时序图工作，并且各个方向的红、黄、绿灯接通时间倒计时显示。有急车来时，将急车强通开关按一次，不管原来信号灯的状态如何，一律强制让急车来车方向的绿灯亮，使急车放行，直至急车通过为止。-The traffic lights at the normal timing control and emergency vehicle through two control methods. Start switch is turned o
gen_act
- Verilog 语言下的 产生ACTIVE信号代码，即讲一段低电平信号转换为闪烁的信号-ACTIVE signal generated code under the Verilog language that speaks for some low-level signal is converted to a flashing signal
pipeline
- 简单的流水线的实现机制，基于verilog语言。-The pipelined implementation, based on Verilog language.
xor4b
- 四为异或门，实现全加器的硬件模块，使用VHDL语言实现，主要适用于初学者实例展示，为初学者提供quartus的实例展示。-4 bits xor gate finished with VHDL language， specifically for greenhands and bachelors who just begin with quartus