资源列表
LED
- 一个非常好的LED程序 包括了LED的三种状态 亮 灭 和闪烁 移植性好 -A very good LED program includes three LED status light blinking off and good portability
Examen
- This program makes a PIC18F4550 read 2 analog inputs and show the value in a LCD 16x2, by selecting the channel to print with a switch
formation
- This a piece I wrote that I used for an old project. This allows an enemy to create a spiral bullet formation.-This is a piece I wrote that I used for an old project. This allows an enemy to create a spiral bullet formation.
lock
- 电子密码锁，实现并行输入，错误报警和密码设置功能，以及兼作门铃使用-Electronic code locks, the realization of parallel importation, error alarm function and password settings, as well as the use of doubles as a doorbell
ledcontrol
- FPGA驱动LED静态显示 --文件名：ledcontrol.vhd --功能：译码输出模块，LED为共阳接法 -FPGA-driven LED static display- File Name: ledcontrol.vhd- Function: decode the output module, LED is connected in a total of Yang
4step2iirfilter
- 用VerilogHDL实现一个阶数为4，两个支路的并行IIR滤波器，可以用同样的方法实现更多支路的滤波器。-With VerilogHDL order to achieve a 4, the two branches of the parallel IIR filter, the method can achieve more with the same branch of the filter.
pcm_slv_top
- 实现了verilog语言的pcm编码功能-verilog pcm module
chengxu
- 60秒倒计时，电子时钟，温度自动控制，可根据温度高低自动报警等；-60-second countdown, electronic clock, automatic temperature control, according to high and low temperature alarm, etc.
Modulator70
- 个人参与的某国家工程并行排序MATLAB程序，用于FPGA的RTLAB仿真，使用Simulink工具生成HDL代码。测试可用。-Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.
DIV_5
- 该源码包包含一个奇分频分频器的Verilog代码及其测试代码。奇分频在许多分频电路中都会用到。-The source code package contains a surprising frequency divider in Verilog code and test code. Odd number of points in the frequency divider circuit will be used in.
SEG
- 采用DE2 实现数码管递增 VERILOG-Using DE2 achieve the digital pipe incremental VERILOG
wgsph_lab
- DDFS Verilog DDFS Verilog DDFS Verilog DDFS Verilog -DDFS Verilog DDFS Verilog DDFS Verilog DDFS Verilog DDFS VerilogDDFS VerilogDDFS Verilog