资源列表
CHENGFAQI
- 本源码是高速并行乘法器的设计源码，开发软件为MAX+PLUS.输入为两个带符号的二进制数-the source is a high-speed parallel multiplier design source, development of software for MAX PLUS. with the importation of two symbols of binary -
div
- VHDL任意整数分频程序，只要讲n换成需要的数字就可以了！
small_fifo
- 同步fifo设计，仿真已通过，用Verilog编写，代码短小，易懂-Synchronous fifo design, simulation has been adopted, written with Verilog, code short and easy to understand
syn_fifo
- A Verilog descr iption of a synchronous FIFO memory circuit
nxn_multiplier
- Verilog module for hardware N x N multiplier using generate keyword.
MAX1076
- MAX1076AD 转换芯片 控制器 VHDL实现-MAX1076AD conversion chip controller VHDL implementation
01
- 二位数值比较器 奇偶校验器 七段显示译码器-Comparison of two numerical control device parity seven segment display decoder
AD0809-VHDL
- ADC0809模数转换器 VHDL 代码，用数码管显示值-ADC0809 ADC VHDL code, with digital display
liangzhu
- verilog 写的 “梁祝”乐曲演奏电路-erilog wrote " The Butterfly Lovers" music concert circuit
frequency---base-on-verilog
- 基于verilog的数字频率计设计(源码)-frequency design base on verilog
paobiao
- 本源码是用verilog编写的FPGA程序，其中包括了数字跑表模块和RS触发器模块。-The source code is written in verilog FPGA programs, including digital stopwatch module and the RS flip-flop modules.
Radix_4
- Verilog for radix algo