资源列表
WERDTEST
- CCD DRIVER 本软件用于线性CCD 传感器时序控制 -CCD DRIVER software for the linear CCD sensor timing control
基于 FPGA 实现的冒泡排序法范例
- 基于 FPGA 实现的冒泡排序法范例,Verilog 的语法.
top_vga
- 产生VGA彩条信号(Verilog 语言）-Generate VGA signal
telephone
- 实现长途电话，市话的计时，还有免费电话 在verilog中用状态机实现-The achievement of long-distance calls, the city of the time, then, there are toll-free number in verilog state machine used to achieve
test_adc_lcd
- test for analog input in 16f876 and out on lcd
lzm_bubble_soft
- 基于fpga实现的冒泡排序，初学者研究资料，希望更深一步的进行研究-Fpga-based implementation of bubble sort, beginners research data, hoping to study deeper
dds32_1
- 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序-Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program
WWDG
- keil 环境下窗口定时器工作的寄存器配置下的实现-Window timer register is configured to work in the realization
inverse_counter
- 利用ALTERA的DE2实现4位可逆计数器，并进行7段译码显示，VHDL编写-4-bit counter with 7-segment display using VHDL
2
- DSP TMS320F283335产生PWM波，占空比50 -DSP TMS320F283335 generate PWM wave, duty cycle 50
led
- DSP 程序，实现led灯闪烁，C55和C54均可兼容，可改变频率-DSP program, led lights flashing achieve
bram_shift_reg_w16x3072
- 使用 xilinx blockram 做连续shift 在图像处理中 做多行缓存很方便-Using blockram Xilinx as a continuous shift in the image processing to do more than the cache is convenient