资源列表
shukongfenpinqi
- 数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。 -NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the
ca_gen
- 此Verilog程序产生用于GPS卫星导航信号的C/A码，输入信号有时钟、时钟使能、复位、给定的卫星编号，输出产生的C/A码。此程序在代码上进行优化，占用了更少的资源。-This procedure generated Verilog for the GPS satellite navigation signals C/A code, the input signal with the clock, clock enable, reset, given the satellite number,
22
- 这个是洗衣机控制器的代码，是用vhdl编写的，只有两个程序，有需要的用户可以下载-This is the washing machine controller code is written in vhdl, only two procedures, there is a need for users to download
CU
- This a example for Control unit-This is a example for Control unit
VHDL_VGA
- VGA的VHDL编程示例代码，对学习VHDL编程帮助很大-VGA programming examples of VHDL code, VHDL programming of great help in learning
New-DS1307
- read clock ds1307 with bascom
lpc11-time16-
- lpc11*8 16位定时器匹配例程程序-lpc 16-bit timer match routine procedures
control
- The Pipeline SPIN model using VHDL
pid
- pid controller design based vhdl code in xilinx code-pid controller design based vhdl code in xilinx code.....................
Serial-port-sending
- 基于FPGA的串口发送程序，用VHDL语言编写，采用状态机的方法，可用串口调试软件进行测试-FPGA-based serial port procedures, using VHDL language, using the state machine approach can be used to test serial debugging software
changewin
- 用verilog实现40比特的串并转换，激励文件同时写在程序中。-Use verilog implementation 40 bits of string and transform, incentive documents written in a program at the same time.
QPSK1
- 基于verilog的QPSK调制的程序，调试通过，有需要可以下载来参考-QPSK modulation-based verilog procedures, debugging through, there is a need to reference download