资源列表
screw
- 一个好用的扰码器，主要用在光纤通信上面。因为为了保持送给光模块的信号不是全1或者全0-A nice scrambler, mainly used in optical fiber communication above. Because in order to maintain the optical module of the signal is not sent to all 1 or all 0
settime_example
- VxWorks, clock_settime() example
KFFT
- dspf2812 自己的fft算法 改进过的-dspf2812 fft algorithm improved
PSKcodeconversion
- 利用硬件描述语言VHDL实现PSK信号相对码和绝对码的转换-Two VHDL programs to realize the PSK signals conversion between absolute and relative code
analog.c
- jfwletjwevmyrejemrukrk iptyik 67koi
CLK_DIV
- verilog HDL写的时钟通用计数分频程序，设置系统时钟，并根据目标时钟，设置分频系数即可得到目标时钟。已实际测试可用。-verilog HDL write clock common procedures for the count and divide, set the system clock, and the root According to the target clock, set the frequency division factor can get the targ
uart_trs_state
- 本程序是串口的FPGA产生程序，希望在此能够给与大家共享-This program is a serial FPGA generator, I hope to give everyone shared this
ep24c02
- C8051F130 实现的 24C02 读写程序-24C02 read and write procedures to achieve C8051F130
MMA7455
- 本程序是通过51单片机驱动MMA7455，程序调试通过！-This program is driven by 51 MCU MMA7455, program debugging through!
c8051f120--UART0
- c8051f120 串口0使用函数，运行成功。你只需在自己的程序中调用其中函数，即可使用串口0通信。-c8051f120 serial 0 to use the function, run successfully. You only need to call in your program where the functions, you can use the serial port 0 traffic.
fulladder
- this is fulladder 1bit with testbench