资源列表
VHDL01
- 全加器仿真程序. 大家可以参考下 ，本人检查无误。无毒。如有问题，请来信咨询。-Full adder simulation program. You can refer to, I check the accuracy. Non-toxic. If you have any questions, please contact us advice.
decoder35
- decoder verilog. it is a 3 t0 5 decoder that compile with modelsim.
BBooth
- 基verilog 布斯乘法器 4位位宽，本人不才，仅做参考-Booth multiplier based verilog
freq_divider
- 一个时钟分频器，可以实现任意整数倍或者分数倍的分频功能。-A clock divider can be an arbitrary integer multiple or fraction of times the frequency function.
Diesel-Engine-Lubricating-System-SCM
- 内燃机润滑系统单片机程序设计，使用汇编语言编写-Diesel Engine Lubricating System SCM
assembly-language
- 一段dsp连接显示器的键盘扫描程序，汇编语言编写而成-Dsp displays a keyboard connected scanner, written in assembly language
JKF.vhd
- pulse framing circuit
traffic
- DE2_traffic_light(in verilog source code)
FIFO
- FIRST IN FIRST OUT Q-FIRST IN FIRST OUT QUEUE
COUNT60
- 60位进制计数器 可将程序下载后进行60进制表现 并应用于电子表运算-60 binary counter can download the program and after the performance of 60 binary operations used in electronic form
a-to-A
- 将字符串转换为ASICII，用于FPGA码表-from strings to ASICII
svpwm
- SVPWM生成,用在电机控制的电压矢量生成，输入为alpha，beta电压，输出为三相占空比-motor control svpwm