资源列表
filter
- TI的dsp c2000的开发中一段软件滤波的程序-TI' s dsp c2000 in the development of a software filtering process
booth
- 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
pb5_pb6_exist
- 说明了在系统上怎么装Wince 且使Wince 5和wince6可以共存不会发生冲突。-Illustrates how the system installed Wince and make Wince 5 and wince6 can co-exist not conflict.
Abus_fifo_ram_V1
- 该模块是基于verilog语言编写的双口ram模块，可将该该模块作为缓存模块使用-surpost ram write/read
lcd-16x2-arduino-lcd-codes
- Source code print caracter to lcd 16x2 from arduino modules
strobe_gen
- 分频功能，clk,reset为输入端口，分频系数10，时钟为25mhz。-Divide function, to obtain the required clock.
crc-ccitt
- CRC校验ccitt的串行功能实现，实现16位CRC校验，校验方式是CCI-function of realize crc ccitt 16BIT
GPRS_SERVERSIDE_PYTHON
- GPRS server side, Python is used... You can monitor temperature
DELAY
- Generic Delay routines written for the AVr microcontroller. Easy to implement long delays and timing functions
Dlatch3
- 基于VHDL的触发器设计。 由一个电平触发的D触发器构成的上下边沿触发器。-Trigger-based VHDL design. Consists of a level-triggered D flip-flops up and down the edge of the trigger.
pid
- 适用于带有采集板卡的电液伺服位移控制系统，通过大量实验确定了较为良好的pid参数，实现精确控制位移。-Electro-hydraulic servo control system applicable to the displacement of the board with the acquisition, through a lot of experiments to determine a more favorable pid parameters to achieve precise c
mapperSharp1(16QAM)
- This the code for the mapper in the verilog code.-This is the code for the mapper in the verilog code.