资源列表
modifiedBoothMultiplier
- verilog code for modified booth multiplication using maxplus2
UniversaRlegister
- 通用寄存器的编程，能对FPGA的学习有更进一步的了解，尤其对初学者帮助多多。-General Register of programming, the FPGA can have a better understanding of learning, especially for beginners to help a lot.
mul
- baugh wooley multiplier with two four bit input and eight bit output
alu
- 用VHDL语言编写的CPU当中的ALU模块，可是实现十条指令-CPU using VHDL languages among the ALU module, but to achieve ten instructions
bcd7seg
- bcd to 7-segment decoder
pwm
- PWM的NIOS II IP核设计源文件，其频率和脉宽均可控-PWM IP core design source files of the NIOS II , It s frequency and pulse-width words can be controlled
snark
- /* $Header: /usr/cvsroot/target/h/wrn/wm/util/port/vxworks/snark.h,v 1.1.1.1 2001/11/05 17:47:17 tneale Exp $ */ /* * Copyright (C) 1999-2005 Wind River Systems, Inc. * All rights reserved. Provided under license only. * Distribution or
2Cpp2
- 单片机开发C语言编写的用数码管显示的流水灯四位数循环显示-The flowing light four-digit cycle
TLC1543-AD-SAMPING
- TLC1543 为A/D转换器芯片，该程序为此芯片的读写程序代码。-TLC1543 A/D converter chip, the program for this chip reader program code.
BianMaQiXiFen
- 位置编码器细分，由两个相位差为90°的信号产生每周期4位置。-Position encoder broken by two 90 ° phase shift of the signal generating every position on.
XB_qudong3
- 实现永磁同步电机速度电流双闭环控制，调制方式SVPWM-Speed current double closed loop control of permanent magnet synchronous motor, modulation mode SVPWM
Uart_receive
- STM32F4系列串口接收函数,，程序已测试通过。-void USART1_IRQHandler(void) //串口1中断服务程序 { u8 Res #ifdef OS_TICKS_PER_SEC //如果时钟节拍数定义了,说明要使用ucosII了. OSIntEnter() #endif if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET) //接收中断(接收