资源列表
rili
- 日历，用于单片机仿真的调试程序，可以自己调节时间-Calendar, microcomputer simulation of debugging, can adjust time
ADC
- a verilog code about dac of audio codec on fpga board.
paral
- 其实是verilog的关于并行的传输的代码，cpld上用的.-paral port
txrx
- vhdl files tav kkkkk fffchkfdjgxjgcmnm-vhdl files tav kkkkk fffchkfdjgxjgcmnmnn
tv_TB
- test bench for A Modern Stream Cipher - Trivium.
VHDL
- 基于FPGA的IIR滤波器的各模块VHDL程序- such as in science and project technique. Compared with FIR digital filter, IIR digital filter can get high selectivity with low factorial.
LCD1602
- 常用的显示芯片LCD1602的C源程序代码，对于初学者易理解。-Common display chip the LCD1602 of C source code, easy to understand for beginners.
DflipflopSource
- Verilog实现的D触发器及其测试，同步异步的代码都具有，而且还拥有测试代码-Verilog implementation of the D flip-flop and test, synchronous asynchronous code, but also have the test code
GIAIMA416
- decode 4 to 16 path display led
pwm
- msp430g2553// Descr iption: A single sample is made on A10 with reference to internal // 1.5V Vref. Software sets ADC10SC to start sample and conversion - ADC10SC // automatically cleared at EOC. ADC10 internal oscillator/4 times sample // (64x
16b_bcd20
- 十六位的二进制转为二十位的BCD码，传给大家供大家分享-Sixteen twenty binary into BCD code, passed to everyone for sharing
Verilog
- 七段数码管译码器.(Verilog)[FPGA]第一个Verilog程序,七段共阴数码管摸索了好几天,终于能完成敲入代码、综合、仿真、绑定引脚至下载的全套工作了 -. 七段数码管的lookup table module SEG7_LUT ( input [3:0] iDIG, output reg [6:0] oSEG ) always@(iDIG) begin case(iDIG) 4 h1: oSEG = 7 b1111