资源列表
testbench模版
- testbench测试模版
33_COMP
- vhdl做的实数比较器，比较简单，但是实用-The real number vhdl comparator, is relatively simple, but practical
DDS
- 基于fpga技术，采用DDS原理产生3MHZ的正弦波。 -Produced with the DDS sine wave 3MHZ.
Counter24VHDL
- 用VHDL语言实现24进制计数，具有清零、控制使能作用。-VHDL language with the binary count of 24, with clear control in enabled.
VrRAM
- 一个简单的RAM设计，包含内容不多，是一个RAM的精简体，可做学习之用-A simple RAM design, including the content much, the essence of RAM is a simplified, to do with learning
N_Separate-frequency-device
- 可以输入0到2的5次方的任意分频的分频器-Separate frequency device
blockdram
- vhdl code for cyclic block
led
- ALTERA公司的FPGA开发板的流水灯显示VHDL程序-LED DISPIAY
enc
- Encoder vhdl code basic implementation
I2C
- 51单片机端口模拟I2C程序读写24C02程序-51danpianji i2c chengxu
vga
- 直接驱动液晶显示器小程序，不通过DA转换，类似点阵操作-Direct drive LCD display applet, not through the DA converter, similar lattice operations
divider
- FPGA 循环拼接除法 循环拼接除法-FPGA Loop stitching DivisionLoop stitching Division