资源列表
counterfour
- verilog code for counter four
VHDL
- DDS产生正弦波（VHDL语言）用DDS产生3MHZ的正弦波,VHDL控制语言-DDS have a sine wave (VHDL language) 3MHZ generated by the DDS sine wave, VHDL control language
contador_0a7
- contador de 0 a 7 que se reinicia
leDPIC
- hai this use for programming Pic
Stepper_motor_fsm
- stepper motor fsm is the fsm for stepper motor. It indicates the states of stepper motor.
test
- 通过检查节点灯的亮灭以及使用方法来确定指示灯的编号。 nesc语言-Check nodes and number of lights to use. nesc
fulladder
- vhdl code for full adder program using libero software.
RAMexio
- verilog 语言的，PWM测试 梯形图速度控制程序新鲜的-verilog language, PWM speed control test procedures fresh Ladder
quanzixongxiyiji-verilod
- 根据日常生活中的洗衣机使用流程设计状态。 空闲——加水——洗涤——排水——加水——清洗排水——甩干——报警 - according to the processes and the use of washing machine in the daily life of the design state. Idle-------- washing water drainage water------ alarm dry cleaning and drainage
Control-of-small-lights
- 一个实用的用VHDL实现控制小灯的程序，可改变小灯闪烁的频率-A practical small lamp with VHDL control program to control the frequency of small lights flashing
Ram_test
- SRAM IS61LV64读写 经检验ok下载板子成功读写-SRAM IS61LV64 reader board successfully been tested ok download reader
CRC
- 在数据通信过程中，数据校验是必不可少的部分，CRC校验是一种高效的检验方式。-In the process of data communication,data verification is an indispensable part, CRC verification is an efficient way to test.