资源列表
clk_gen
- 基于vhdl的分频器模块设计，已经经过调试，可直接调用-Divider vhdl module based on the design, debugging has been directly call
less
- Less for VHDL Project
clkdiv
- 初学者一个比较容易入门的FPGA verilog 二分频实验。-Relatively easy for beginners to get into a FPGA verilog two-way experiment.
spi
- sirve para programar el spi
20x4
- Interfacing of 20x4 LCD with Microcontroller
RS485
- 一个简单的可实现单片机485主从通信的程序-one simple master-slave RS485 communition procedure
CHAP14_1
- 二阶系统的仿真，并且为PID阶跃响应下下快速稳定-Second-order system simulation, and for PID step response is fast and stable
simple_test
- This a vhdl code for colour converter fpga code for testing shape_gen code-This is a vhdl code for colour converter fpga code for testing shape_gen code
cfq8
- 基于Quartus仿真软件verilog语言的八位二进制乘法器，用于八位二进制乘法运算。-Based on Quartus simulation software of eight binary multiplier, verilog language used in eight binary multiplication.
jkff_behav.v
- This is JK-FF in Behavioural Style.
bujindianji
- 内容：1、本程序用于测试4相步进电机常规驱动 2、需要用跳帽或者杜邦线把信号输出端和对应的步进电机信号输入端连接起来 速度不可以调节的过快，不然就没有力矩转动了 -Contents: 1, the procedures used to test conventional 4-phase stepper motor driver 2, need to jump cap or t
handshake
- Handshake module detection