资源列表
clk_gen
- 基于vhdl的分频器模块设计，已经经过调试，可直接调用-Divider vhdl module based on the design, debugging has been directly call
less
- Less for VHDL Project
clkdiv
- 初学者一个比较容易入门的FPGA verilog 二分频实验。-Relatively easy for beginners to get into a FPGA verilog two-way experiment.
20x4
- Interfacing of 20x4 LCD with Microcontroller
RS485
- 一个简单的可实现单片机485主从通信的程序-one simple master-slave RS485 communition procedure
spi-c
- 这种SPI程序用51单片机的I/O口线很好模拟的,仔细看芯片的文档,下面这个是用在NRF905的-failed to translate
MSP430F261_adc12
- msp430F2616 code for ADC12
CHAP14_1
- 二阶系统的仿真，并且为PID阶跃响应下下快速稳定-Second-order system simulation, and for PID step response is fast and stable
simple_test
- This a vhdl code for colour converter fpga code for testing shape_gen code-This is a vhdl code for colour converter fpga code for testing shape_gen code
cfq8
- 基于Quartus仿真软件verilog语言的八位二进制乘法器，用于八位二进制乘法运算。-Based on Quartus simulation software of eight binary multiplier, verilog language used in eight binary multiplication.
jkff_behav.v
- This is JK-FF in Behavioural Style.
handshake
- Handshake module detection