资源列表
基于74hc165的获取按键的c程序
- 基于74hc165的获取按键的c程序，经过测试，程序很简单明了,Access keys 74hc165 based on the c procedures tested, the procedure is very simple and clear
led_keyboard
- 用verilog语言实现键盘的移动扫描，这是基于ise实现的。 -Verilog language keyboard with a mobile scanner, which is based on the ise to achieve.
counter
- 一个用数码管自动计数的verilog程序，DE2开发板实现-An automatic digital control procedures verilog count, DE2 development board implementation
cordic
- VHDL写的通用调制解调器的核心程序，通过调试 无错无警告-VHDL generic modem to write the core of the procedure, through no fault debugging without warning
StateMachine-based
- FPGA上的利用状态机实现的分频的verilog程序-verilog source code StateMachine-based for FPGA
UART
- 基于NIOS2的串口初始化设计程序，在应用中只要加上这个初始化就可完成所有的初始化任务-Based on the serial port initialization NIOS2 design process, in applications, coupled with this initialization can be completed as long as all of the initialization task
VndingMachine
- 1．机器有一个投币孔，每次只能投入一枚硬币，但可以连续投入多枚硬币。机器能识别的硬币金额为1元，5角和1角。顾客可选择的饮料价格有1元，1元5角，2元三种。每次只能售出1瓶饮料。 2．购买饮料时先选择饮料价格再投币，当投入的硬币总金额达到或超过饮料价格后，机器发出指示信号并拒收继续投入的硬币。顾客投币后，按动确定键，机器将发出饮料和找零硬币，若所投金额不足，则发出欠资信号指示。在欠资情况下，顾客可以继续投币购买，也可按取消键，机器将退出所投入的全部金额。 3．顾客投入硬币之后，如果未按确定键而
AdditionCounter
- 一个带有异步复位和同步时钟使能的十进制加法计数器-Asynchronous reset and synchronization with a clock enable decimal addition counter
zq_100us
- 利用VHDL实现偶数分频，设计了一种能够实现等占空比的任意偶数分频、等占空比任意奇数分频、不等占空比的任意半整数分频的较为通用的分频器,并通过QuartusII进行了功能仿真。 -Use VHDL to achieve an even frequency, designed to achieve such a duty cycle of any even frequency, such as the duty cycle divide any odd number, ranging from
AB-4F
- 基于CPLD 的四倍频辩向电路设计-24位计数 8位单片机数据输出-Based on the CPLD optical pulse encoder signal multiplier circuit design
johnson_count_tb
- JHONSON COUNTER TEST BENCH
RAM_Delay
- 利用块RAM实现数据延时，ab两路数据的位宽都是32位，a路延时16个时钟，b路延时8个时钟-Using block RAM data latency, ab two way data bits wide is 32, a way to delay 16 clock, eight clock delay b road