资源列表
angle
- verilog设计的求复角的源代码 通过仿真验证的-verilog design for phase
final-light
- 跑馬燈喔喔喔喔簡易跑馬燈設計快下載 -Marquee Marquee Wowowowo simple design fast download
simpleLed.vhd
- LED BLINK TEST for FPGA
constituent_encoder
- vhdl code for constituent encoder
vhdl-delay
- vhdl延时程序,源程序，已调试，可以用-VHDL delay program
RAW2RGB
- 数字图像处理，ccd，cmos rawtorgb-raw to rgb
DFF1
- DFF1开发 半加器 超好用的 不信你们试一试呀-DFF1 development of half adder Chaohaoyong do not believe you try ah
clkdiv
- 这是一个FPGA任意分频的很经典的VHDL程序，希望能对大家有帮助-This is an arbitrary frequency FPGA VHDL program of classic, I hope you can help
a_compare_with_b_vm
- 用Verilog描述了一个比较器,输入a和b，当a>b时，输出为a，反之，输出为b-descr iption a comparator by Verilog , the input a and b, when a> b, the output is a, the other hand, the output is b
danpiaji
- 单片机8255A的控制字的用法的程序设计-Single chip computer 8255 a control word usage programming
FTMQuadDec
- K60 FTM正交解码 做飞思卡尔智能车的一定会用到-K60 FTM
LED_loop
- 8个发光管间隔200ms由上至下，再由下至上，再重复一次，然后全部熄灭再以300ms间隔全部闪烁5次。重复此过程。-8 arc tube 200ms interval top to bottom, then the bottom, repeat, and then all went out again with 300ms interval flashes all five times. Repeat this procedure.