资源列表
clk_div
- Clock division document
10010
- verilog实现序列10010检测-verilog to achieve detection of sequence 10010
Demultiplexer
- 解复用器，很好很强大的程序 解复用器，很好很强大的程序-DEscr iptION : Demultiplexer -- Width: 8 -- Number of terminals: 4 -- Output enable active: HIGH -- Output active : HIGH
zhuan2_10
- 用于FPGA/CPLD开发的2进制转换成BCD码的程序。-For FPGA/CPLD development of two binary into BCD code procedures.
bqtize
- 绝对量化子程序 《数字信号处理教程——MATLAB释义与实现》 绝对量化子程序-Absolute quantification procedure " digital signal processing tutorial- MATLAB Interpretation and Implementation" absolute quantification subroutine
rtl
- 基于verilog的FPGA新型跑马灯程序设计-led run
lcd1062
- 通过PIC16F877A控制LCD1062，从而实现液晶显示。-By PIC16F877A control LCD1062, in order to achieve liquid crystal display.
binary_adder_tree_vhd
- This an reconfogurable binary Adder and this is the base for another modules in vhdl
johnson
- johnson计数器是一种同步计数器，每一次之变化一位，具有最简的组合逻辑电路。-johnson counter is a synchronous counter, each followed by a change, with the most simple combinational logic circuit.
crc32
- 循环冗余校验码，CRC32算法的Verilog代码-Cyclic redundancy check code, CRC32 algorithm Verilog code
display
- 通过单片机显示汉字，原理是将编码输入，由单片机相关模板进行显示-the function is display the Chinese word
S12shurubuzhuo
- S12单片机利用TIM定时器的输入捕捉功能实现脉冲计数。-S12 MCU use TIM timer input capture function realizing pulse counting.