资源列表
CordicverilgHDL
- 实现cordic算法，输入数据为16位，为提高精度，输出为20位。-achieve cordic algorithm, the input data for the 16, to increase accuracy and output 20.
yangwenli
- 计费器设计中速度控制模块、里程计数模块、计费计数模块vhdl源代码-accounting device design speed control module, the mileage counter module, billing module count vhdl source code
control9851
- AD9851的vhdl串行控制程序（9851系统时钟内部指定）-AD9851 vhdl the serial control procedures (9851 designated internal system clock)
GenCrc1
- 并口硬盘标准PATA6的CRC效验码的vhdl代码-Parallel hard disk standard PATA6 the CRC code well-tested code vhdl
std_cf_1c20
- Altera公司开发板1c20 CF卡通用例程（初始化、读、写、测试等）-Altera Corporation development board 1c20 CF cartoon with routines (initialization, reading, writing, testing, etc.)
std_cf_1s40
- Altera公司开发板1s40 CF卡通用例程（初始化、读、写、测试等）-Altera Corporation development board 1s40 CF cartoon with routines (initialization, reading, writing, testing, etc.)
std_cf_2s60_ES
- Altera公司开发板2s60 CF卡通用例程（初始化、读、写、测试等）-Altera Corporation development board 2s60 CF cartoon with routines (initialization, reading, writing, testing, etc.)
CommandResponse
- verilog语言写的sdram控制器—命令响应模块代码，经过测试，逻辑正确，可编译，可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated
VHDL.fifo
- 在网上找到的通用存储器vhdl代码库，觉得挺好用的。-the Internet to find the common memory vhdl code library, feeling very good use.
tom08
- SRAM 视频采集测试程序 读写时序控制 为解决时钟切换而做的测试程序-SRAM test sequential read and write control procedures to resolve the clock switching out of the test procedure
fft_512
- 由system generator生成，可供参考-generator generated by the system is available for reference,
fq_divider
- 分频器-Divider ..