资源列表
1_070116141639
- verilog编程ps2接口设计,基于fpga的设计-verilog ps2 Programming Interface design, the design based fpga
vhdl_led
- 7 段数码管实验（包括两个实验） ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０—7，-seven of the digital control experiments (including two experimental), the digital control of a Test : Dynamic scanning approach to the eight digital control "at the same time" show 0 -7
VHDLnf
- VHDL实现任意整数分频，--只要把n设置成你要分频的数值就可以了-VHDL arbitrary integer frequency, -- n as long as you want to set the frequency of the numerical breakdown on the
1_061026140305
- 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.-FPGA-based I2C bus simulation, using verilog HDL language. - Based on the FPGA I2C main line simulation, verilog uses the HDL la
chuanbingzhuanhuan
- VHDL代码，仿真通过，变异可以，下载变成文件，但需要修改，串并转换-VHDL code, through simulation, the variation can be downloaded into a document, but need to change, and change series
ps2_lcd_1602
- 与PS2的通信，PS2按键值发给LCD显示，VHDL语言。-communication with the PS2, PS2 keys to the value of LCD Display, VHDL.
dig_clk_lcd
- 数字钟的实现，由LCD动态显示，VHDL语言实现-the realization by the dynamic display LCD, VHDL
dianzheng6.2banben
- 8*8点阵的实现，循环显示vhdl四个字母-8 * 8 lattice the realization cycle shows vhdl four letters
qiangdaqi4ren7.1
- 四人抢答器的实现，主持人按键清除按键，按开始键，100秒倒计时答题时间-four Responder the realization host keys to remove the keys, according to begin key 100 seconds to answer in the countdown time
pingche
- 简易数字频率计，数码管显示，VHDL语言-simple digital frequency meter, digital control, VHDL
mimasuo2S50
- 8位密码锁的实现，初始状态默认为密码正确，密码输入正确方可设密码，以后必须按对密码才可重设-8 password lock the realization of initial state defaults to the correct password, the password can input the correct password. After the password must be re-established before
Bintograyconverter
- 二进制到格雷码转换ASD ASD ASD-binary Gray code conversion to ASD ASD ASD ASD ASD