资源列表
pinlv
- 基于单片机与CPLD的 等精度频率计,VHDL语言
s_fifo
- 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench
CompilerOptimizations
- To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level o
keyboad
- VHDL 的4*4键盘代码
ram
- VHDL 编写的RAM例子
Vhdl_Simulation_With_Modelsim
- Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.
generic_avalon_sram
- 一个比较有参考价值的sram IP核,对SOPC感兴趣的人士有一定的指导意义!该程序是采用avalon总线,可以直接内嵌进SOPC Builder。
AccountSystemOfPublicPhone
- 采用Verilog HDL硬件语言设计,实现基本的公用电话计费功能,设计完整.
pinlvji
- 频率计,vhdl语言, ispDesignEXPERT
DDS-2
- 用FPGA实现DDS的原理图,结构清晰,采用总线方式与外部单片机通信
Ymeasure
- 基于FPGA的相位测量原理图,通过对正弦信号过零比较进入FPGA,测量相位差。可用于测量导纳等应用中。
cpld(huaqi)
- 上海外滩看到的最大的LED显示屏的内核源代码,主要是完成视频信号的远距离传输的编解码与接口转换