资源列表
meng
- for lattice s vhdl -for lattice s vhdl
abel-hdl
- lattice的abel-hel开发文档，对cpld开发的朋友会有用-the lattice-CAS documentation, the development of cpld be friends with
ispLEVER培训教程
- ispLEVER是LATTICE的CPLD、FPGA继承开发环境-ispLEVER CPLD, FPGA development environment succession
sdram
- sdram控制器 这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, a
baud
- vhdl 很好用于串行通信. 三个模快,发生时钟,发送和 接收过程-VHDL good for serial communication. Three die fast, occurred clock, sending and receiving process
VHDL的编程实例
- 别人的一些常用的VHDL源代码,希望对各位有用!-some others used the VHDL source code, and I hope to you and useful!
synth_fft_fpga
- 用fpga实现fft-achieve fft
PCI_144
- -- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library --- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library
各段程序
- 具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。 -with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
Digital_030423
- 服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).-server board controller is contained in the AHDL procedures, including schematic compiler, the use EPM7128 (CPLD).
control step motor
- 步进电机控制，控制器,控制电机的VHDL源程序-stepper motor control, controllers, motor control VHDL source
Verilog DHL数字钟
- 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock