资源列表
CH5CH4CH2CH1VHDL 数字电路参考书所有程序5
- CH4CH2CH1VHDL 数字电路参考书所有程序5-CH4CH2CH1VHDL digital circuit reference all proceedings 5
CH6CH4CH2CH1VHDL 数字电路参考书所有程序4
- CH4CH2CH1VHDL 数字电路参考书所有程序5-CH4CH2CH1VHDL digital circuit reference all proceedings 5
CH7CH4CH2CH1VHDL 数字电路参考书所有程序7
- CH4CH2CH1VHDL 数字电路参考书所有程序7-CH4CH2CH1VHDL digital circuit reference all proceedings 7
CH8CH4CH2CH1VHDL 数字电路参考书所有程序8
- CH4CH2CH1VHDL 数字电路参考书所有程序8-CH4CH2CH1VHDL digital circuit reference all proceedings 8
CH9CH4CH2CH1VHDL 数字电路参考书所有程序9
- CH4CH2CH1VHDL 数字电路参考书所有程序9-CH4CH2CH1VHDL digital circuit reference all proceedings 9
CPLD的跑馬燈
- cpld的入门交流:CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言遍的-cpld entry exchange : CPLD 5,250 cpld an easy-to-use test circuit using VHDL times the
ref-sdr-sdram-verilog
- 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
发布15个Altera的IP的源码
- ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
add_full_n
- 该程序实现的是n位全加器,首先用与非门实现一位全家器,最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family - and finally realize the full n-bit adder.
sub_full_n
- 该程序实现的N位全减器,首先实现一位的减法器,之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.
counter10
- 该程序实现的是10进制的计数器,具有置位复位的功能。-the program is the band of 10 counters, with the home-reset function.
codestream
- 设计一个模块,从一个窜行数据流里检测出码流“11100”,这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch