资源列表
Booth_Multiplier
- 布斯乘法器的VHDL程序,下載後直接解壓縮複製貼上到你的EDATOOL就可以.-Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can.
frame_sync
- 帧同步模块的Veriolog源码。 在ModelSim下的一个工程。有测试文件。-frame synchronization module Veriolog source. The ModelSim of a project. A test document.
hamin0132
- 汉明码的编结码模块，用verilog写成，为Modelsim下的一个工程。-series guitar code modules, using Verilog languages, as Modelsim of a project.
QPSK2154
- QPSK的VERLOG源码，在MODELSIM下的一个工程，有测试向量。-QPSK VERLOG source of the MODELSIM of a project, test vector.
dll11254
- 数字琐相环DPLL的VERLOG代码，MODELSIM下的工程，有测试文件-digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
crc3321
- CRC循环校验码的VERILOG源文件，在MODELSIM下的一个工程。-Cyclic Check Code VERILOG source, the MODELSIM of a project.
parity2258
- 奇偶校验码的VERILOG源码，为MODELSIM下的一个工程。有测试文件。-parity VERILOG source code for MODELSIM of a project. A test document.
EDATOOL
- EDA的工具介紹(WORD檔)<沒有解壓縮密碼>-introduced EDA tools (Word stalls) lt; No extract passwords gt;
Full_Adder
- 全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼-full adder and the VHDL_CODE TEST_BENCH not extract passwords
time_display&alarm_clock
- 此为在实验板上通过的时钟闹铃程序，源码分别用ASM和VHDL描叙，但两程序功能不同。-this experiment for the board through the alarm clock procedures were used ASM source VHDL and depicts, but the two procedures different functions.
program_all
- 此文件里为我多年收集的子程序模块源代码，对于初学者很适用。用多种语句描叙，有常用的基本电路模块描叙。-this document for many years I collected subroutine module source code, the application for beginners. Using a variety of statements depicts a common basic circuit module depicts.
I2C_read
- I2C读程序，通过状态机描叙,仿真达到要求-I2C Reading, depicts through the state machine, called Simulation