资源列表
threeflift
- 三层电梯控制器VHDL源程序，是本人的毕业设计-three VHDL source elevator controller, I was the graduate design!
liang_zhu_music_player
- 用Verilog HDL 语言编写的播放梁祝的程序-with Verilog HDL language broadcast of the proceedings Butterfly Lovers
GWDVPB
- 基于VHDL语言的高精度频率计的设计,已通过实验测试-based on VHDL frequency precision of the design, experimental test
VHDL_Yifeng_Ke
- 原版VHDL语言教程 我也是在网上搜索到的，很经典 好东东不敢自己独享！-original VHDL Guide I am also in the online search of the classic good Dongdong dare not stay!
100vhdl
- 100 VHDL programming examples 100 VHDL programming examples 100 examples of VHDL programming -100 VHDL programming examples hundred pro VHDL gramming 100 VHDL programming examples exampl es 100 VHDL programming examples hundred VHDL progr amming exam
userbscan
- xilinx FPGA上使用jtag接口作为用户IO的源码。支持任意位宽度。-Xilinx FPGAs use JTAG interface as user IO source. Support for arbitrary bit width.
yibutongxin
- 本程序是用VHDL语言实现异步通信控制器， hao1.vhd为主程序，hao1.scf为仿真波形-this procedure is used VHDL asynchronous communication controller, mainly hao1.vhd procedures, hao1.scf for simulation waveforms
xiaolizi1588
- ic读卡器 能读ic电话卡并按时记费-ic reader can read ic phone cards and charged fees on time. .
8051IPCORE
- VHDL写成的8051IP核，仔细看能有不少收货-written in VHDL 8051IP nuclear, look very carefully to have a receipt
bicount
- 完整的双向计数器VHDL 程序 大家参考-integrity of the two-way counter VHDL reference procedures
qep_data_bus
- 基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的-address bus interface based on the four frequency signal encoder interface FPGA Verilog HDL
eclock
- MAXPULS II 下VHDL实现多功能电子钟的源代码，包括时钟，秒表，日历等多种功能-MAXPULS II under VHDL multifunctional electronic clock source code, including the clock, stopwatch, multiple functions such as calendar