资源列表
EP1C3_12_5_RSV
- 基于ＦＰＧＡ的数字存储示波器，用ＶＨＤＬ实现的，压缩包里是Quartus工程。AD采样送进FPGA，存入SRAM后用DA在普通示波器上可以显示。-FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display.
sram_060803
- SRAM的读写代码，对SRAM进行了乒乓操作，用VHDL语言进行设计，很有参考价值，甚至可以直接复制代码来进行自己的设计-SRAM read and write code, ping-pong operation carried out on the SRAM, using VHDL language design, of great reference value, or even directly copy the code to carry out their own designs
OK-fifotest-important_low_to_high
- 高速到低速的FIFO乒乓操作，已经测试通过-Achieve the pingpang operation of FIFO
Encoder_SSI_Veryilog
- 本文详细描述了SSI协议的通讯格式、原理及应用电路,并采用verilog语言实现了SSI通讯协议.设计实用电路并实现了与绝对值编码器的通讯-SSI protocol described in detail the communication format, principle and application circuit, and use verilog language of the SSI protocol. Practical circuit design and implementat
hdlc
- HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
I2C
- Verilog 实现 IIC 源码,包括各个时序信号的详细描述-Verilog code for IIC
TCL2543
- 基于FPGA的TLC2543控制器,采用状态进行控制ADC进行转换-The TLC2543 controller based on FPGA, using state control of ADC conversion
CDC-Protocal(cn)
- 汽车音响CD机通讯控制协议CDC协议中文版。-CDC PROTOCAL
costas_loop
- 集中式插入式帧同步发的verilog源代码-concentrative inserted frame sync
bouncing_ball
- 使用verilog硬件描述语言实现经典游戏反弹球（打砖块）。-Verilog hardware descr iption language using the classic bouncing ball game (Arkanoid).
1024FFT-verilog-hdl
- 基于spartan 3e 的IFFT算法verilog HDL程序-Based on the verilog 3e Spartan IFFT algorithm of HDL program
xapp859_rtl
- xilinx PCIE IP核 包括ddr2 memory interface ML555开发板-xilinx PCIE IP cores containing ddr2 memory interface can be used on ML555 development kit