资源列表
VHDLexample
- here is a VHDL example
vending_machine
- 一个简单的自动售货机控制器，投足25美分便发糖果，并且自动找零-A simple vending machine controller, 25 cents will be made every move she makes candy and give change automatically
clock_tb.v
- a verilog code for a clock.
shumadisplay
- 一种用verilog写的数码显示程序，编译通过，可下载到fpga中-program of shumadisplay,write by verilog language
freaq_meter
- It s a code in VHDL for freq_meter
ASSIGNMENT_1
- its an assignment given to us on 2 way traffic controller
GeneradorFunciones
- Sine signal generator with the following I/O entity sinewave is port (clk :in std_logic dataout : out integer range -128 to 127 ) end sinewave -Sine signal generator with the following I/O entity sinewave is port (clk :in std
BCD
- ROM vhdl for binary to BCD
count-for-6-data
- count data entry for 6 data and convert to 32bit floating point in verilog code.
counter
- 一個三角波產生器 適用於PWM上的使用-A triangular wave generator is suitable for PWM use
fir16.v
- 16阶FIR滤波器设计的verilog代码-Verilog 16-order FIR filter
rom
- vhdl veri log rom file