资源列表
Verilog数字系统设计教程(第2版)
- 主要针对用VHDL语言开发FPGA编程学习资料，简单实用。(Mainly for the use of VHDL language development FPGA programming learning materials, simple and practical.)
Vivado 2016.1 安装流程
- Vivado是 Xilinx新一代针对7系列及后续 系列及后续 FPGA 的开发平台。 Vivado 2016.1是官方首个支持 是官方首个支持 win10的版本。(Vivado is the new generation of Xilinx for the 7 and subsequent series and subsequent FPGA development platform. Vivado 2016.1 is the official first support, is the of
SV_AVMM_DMA_DDR3_128M
- altera公司avmm借口pcie dma设计实例，在实际工程中应用成功(Altera avmm, Inc., PCIe DMA design example, applied successfully in actual engineering)
ddr3control
- 8位突发长度，一次64bit数据读写，MIG核(DDR3 controll implimention)
fpga
- pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)
apb
- APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
PCITest
- 通过在FPGA内部的数据源产生40Mbps的数据，FPGA对数据进行缓冲后，每52ms左右向主机发出一次中断，请求进行DMA传输，每次DMA的大小为228352字节。另附C++上位机软件代码(By generating 40Mbps data from the data source inside the FPGA, the FPGA buffers the data and sends an interrupt to the host every 52ms or so, requesting
ad9516_peizhi
- 实现ad9516的配置(11/5000 Implement the configuration of ad9516 Implement the configuration of ad9516)
MIL-STD-1553B代码
- FPGA实现1553B编解码器功能 Verilog语言(FPGA implementation of 1553B codec function, Verilog language)
DS1302
- AX301开发板上配置了一片实时时钟（RTC）芯片，型号DS1302。学习和掌握DS1302的基本原理，并完成电子时钟的设计。 要求：（1）用数码管显示时，分，秒； （2）有时间预置功能；(The AX301 development board is configured with a real-time clock (RTC) chip, model DS1302. Study and master the basic principles of DS1302, and complete
xapp1014-xilinx-sdi
- xilinx FPGA实现SDI接口输入输出(SDI in/out with xilinx FPGA)
232串口程序
- 实现FPGA平台下串口通信，支持波特率选择，测试稳定。使能信号下降沿有效(Serial communication, support baud rate selection)