资源列表
ASKDASK
- ask调制,基于VHDL仿真平台,解调同样给出,此程序经过验证-ask modulation, based on VHDL simulation platform, demodulator is the same, this procedure proven
FSKDFSK
- fsk调制与解调,此程序经过验证,可以运用,通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use
基于FPGA的李沙育图形发生器
- 这是一个用MAX+PLUSII开发FPGA(1K30器件)开发的李沙育图形发生器(硬件描述语言部分)。-This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware descr iption language).
32位-33M 从模式(target)PCI接口参考设计_lattice
- 32位/33M 从模式(target)PCI接口参考设计,Lattice提供。由于PCI时序较复杂,此设计仅能供参考-32 / route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
8051参考设计_Oregano System 提供_vhdl
- 8051参考设计,与其他8051的免费IP相比,文档相对较全,Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
CRC校验参考设计_xilinx_verilog
- IEEE 802.3 Cyclic Redundancy Check参考设计,xilinx提供-IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx
CRC校验参考设计_xilinx_vhdl
- 可配置CRC参考设计 xilinx提供的VHDL-configurable CRC reference design for Xilinx VHDL
dds_quicklogic
- 直接频率合成,Quicklogic提供,部分源文件是Quicklogic 专用文件-direct frequency synthesis, pioneered provide some source document is dedicated ESP
I2C总线控制器 altera提供-VHDL
- I2C总线控制器 altera提供的VHDL的源程序代码-I2C Bus Controller ALTERA the VHDL source code
PCI总线仲裁参考设计,Quicklogic提供
- PCI总线仲裁参考设计,Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code
PLD与8051接口的参考设计 Xilinx提供_vhdl
- PLD与8051接口的参考设计 Xilinx提供的verilog源代码-PLD 8051 interface with the Xilinx Reference Design for the Verilog source code
ZBT SRAM控制器参考设计_verilog_xilinx
- ZBT SRAM控制器参考设计,xilinx提供,(ZBT SRAM是一种高速同步SRAM)-ZBT SRAM controller reference design for Xilinx (ZBT SRAM, a high-speed synchronous SRAM)