资源列表
scc
- It is a scanner Verilog code for 4*4 matrix keypad system. It reads the key which is pressed.
lanqiu-30
- 30秒计时器,有0~30顺数计数，个位，十位分开写-30 miao ji shi
fenpinVHD
- 任意分频的VHDL 任意分频的VHDL-Any sub-band frequency VHDL any sub-sub-frequency VHDL arbitrary VHDL
add
- 16位的加法器，全加器，有效的利用了门电路用以实现全加器的进位-16 of the adder, full adder and effective use of the gate for the binary full adder
digital_filter
- 数据滤波功能，可以配置滤波的宽度,或者向后推几个时钟-The data filtering function, can configure the filter width
read_data
- 撲克牌遊戲之下層模組,完整的程式碼,讓初學者快速學習,輕鬆編寫程式,將程式改寫後,成為你的程式! -The lower module poker game, complete code, for beginners to learn quickly, easily write programs, after rewriting the program, to be your program!
uart_tx
- UART 发送模块，UART底层的发送块，包含起始位，数据位，校验位，验证通过-UART transmit module，contain start bit，data bit，check bit. have passed verification
adder_n_bits
- vhdl entity adder of two words of nbits.
daddf
- DAC0832 接口电路程序，今天上午本人已验证，-DAC0832 interface circuit procedure, this morning I have verified,
biaojueqi
- 七段显示译码器，在学习中是一个经典案例，值得认真学习-Seven segment display decoder, in a classic case study worthy of serious study
clock
- 大学生篮球比赛30S计时器-30S college basketball game timer
sqrt
- VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG descr iption of open square modules nuclear root operation is the core computing module FPGA or ASIC design.