资源列表
yanshi_31
- 一路信号计数延时器。可根据此文件修改延迟时间。-One signal count delay. Delay time can be modified according to this document.
BUFG_CLKDV_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
4by4
- 4输入，4输出，clos网络所用，有利于连接处理器和处理器，处理器和存储器传输数据。-4 inputs, 4 outputs, clos network use is conducive to connecting the processor and processor, processor and memory to transfer data.
attachments_15_02_2011.
- barrel shifter in vhdl coding
key_led
- _key_led_without_debounce 轻触开关S1~S4 控制LED 亮灭，无按键去抖-_key_led_without_debounce touch switch S1 ~ S4 control the LED light off, no key debounce
DataMemory
- datamemory code in verilog for pipeline processor
8155-timer
- 该程序是 8155定时程序，该程序是由汇编语言编写，可在单片机最小系统上运行。-The program is the 8155 regular program, the program is written in assembly language can be run on the smallest single-chip system.
make-file-vcs.tar
- this the verilog code of 4:1 mux and i have used case statement to explain the logic of this mux-this is the verilog code of 4:1 mux and i have used case statement to explain the logic of this mux
terasic
- 台湾友晶科技大多数开发板光盘资料下载地址，Altera部分ftp地址，非常实用的。友晶有网站中，需要注册个账号登陆进去才可以下载，在友晶中国大陆与其他国家和地区账号是分开的，两个地方都可以注册，都可以登陆进去-Terasic and Altera download site address
beep
- 蜂鸣器输出报警声实验 滴。。滴。。滴。。 -Buzzer output alarm sound experiment Drops. . Drops. . Drops. .
ccd
- 这个爱马仕请认真书写上传资料的详细功能、包含内容说明(至少要20个字)。尽量不要让站长把时间都花费在为您修正说明上-this is a qudong
New-Compressed-(zipped)-Folder-(4)
- verilog code for sequence detection implemented on FPGA using quartus simulator